1. Technical Field
The present invention generally relates to the field of flat panel display and, particularly, to a display panel with half source driver (HSD) structure and a display data supplying method thereof.
2. Description of the Related Art
Flat panel display devices such as liquid crystal displays (LCDs) and plasma displays have the advantages of high image quality, small size, light weight and widely application, and thus are popularly applied to the consumer electronic products, such as mobile phones, notebooks, desktop display and television, and have gradually replaced the traditional cathode ray tube (CRT) display as the main trend in the display industry.
Referring to FIG. 1, showing a conventional display panel 10 with half source driver (HSD) structure. The display panel 10 includes two gate on array (GOA) circuits 11, 13, a plurality of data lines S1˜S4, a plurality of first gate lines G1, G3, G5 and G7, a plurality of second gate lines G2, G4, G6 and G8, a plurality of first pixels 122 and a plurality of second pixels 124. Each of the data lines S1˜S4 is for receiving a plurality of display data and for transmitting the display data to the first and second pixels 122, 124 electrically coupled thereto. The first and second pixels 122, 124 electrically coupled to the data lines S1˜S4 respectively are disposed at two opposite sides of each data line. The first gate lines G1, G3, G5 and G7 are for, in turn, transmitting a first gate driving signal generated from the GOA circuit 11 to enable the first pixels 122 to receive the display data from the data lines S1˜S4. The second gate lines G2, G4, G6 and G8 are for, in turn, transmitting a second gate driving signal generated from the GOA circuit 13 to enable the second pixels 124 to receive the display data from the data lines S1˜S4. The first pixels 122 and the second pixels 124 arranged in the same pixel row are the pixels for displaying the same color (e.g., red, green or blue).
Referring to FIG. 2, showing timing diagrams of multiple signals of the display panel 10. In particular, timing diagrams of a data-loading signal (LD), a display data signal (source OP data), a polarity signal (POL) and a vertical start pulse signal (VSTL) in an Nth frame and an (N+1)th frame are illustrated in FIG. 2.
It is found from FIGS. 1 and 2 that a data inversion used in the display panel 10 is dot inversion. The polarity of each of the data lines S1˜S4 is inversed at each line period of every frame image, resulting in the power consumption of the data lines S1˜S4 is relatively high.